1. Field of the Invention
The present invention relates generally to an electronic memory device and more particularly, to a Synchronous Dynamic Random Access Memory having an improved architecture for operating in the burst mode without substantially increasing the size of the Memory.
2. Description of the Prior Art
Dynamic Random Access Memory (DRAM) is utilized in various electronic systems for storing large amounts of digitally encoded information. The speed of DRAMs have become more critical since the electronic systems that utilize these devices are operating at ever increasing speeds. This requires DRAM devices that have much faster access times for both reading and writing functions.
A number of techniques have been developed to increase the performance of these devices. One such technique is known as "pre-fetching", which is disclosed in U.S. Pat. No. 5,285,421, entitled SCHEME FOR ELIMINATING PAGE BOUNDARY LIMITATION ON INITIAL ACCESS OF A SERIAL CONTIGUOUS ACCESS MEMORY, issued on Feb. 8, 1994. The "pre-fetching" technique is usually utilized in a special type of DRAM known as a Sequential Dynamic Random Access Memory (SDRAM). In these types of devices, successive memory locations are accessed which are often adjacently located.
The "pre-fetching" technique takes advantage of the sequential access pattern by latching additional data into a register, in addition to the data corresponding to the specified address. The additional data is located in addresses adjacent to the specified address. By storing the additional data fetched in the register, subsequent data may be made available in the time it requires to read the register, which is shorter than the initial access time. Thus, the total time for completing a number of sequential accesses is significantly reduced.
Another technique known as "burst mode" is disclosed in U.S. Pat. No. 5,392,239 to Margulis et al., entitled BURST MODE DRAM, issued on Feb. 21, 1995. This technique involves a large block of data to be either rapidly read or written to a group of consecutive addresses. The use of consecutive addresses increases DRAM performance because the addressing scheme can be simplified. This technique only requires a single initial address to be specified in which additional addresses can be generated by incrementing the initial address. Thus, it is no longer required to send an entire address with every word of data. Margulis implements the burst mode technique by utilizing a burst mode detector, counter and buffer.
SDRAM devices and other types of memory devices are requiring faster access times. The clock frequency of, for example, a 256M SDRAM is expected to be between 200 MHz and 250 MHz. In order to realize such a device, a 2 bit pre-fetch is usually required. These clock speeds also require the data to be transferred to and from the device utilizing the "burst mode" technique, where there is one data transfer per clock cycle (4-5 ns). The burst length or number of clock cycles is usually determined by a SDRAM Mode Register.
In SDRAM devices, there are two different burst types, which are determined by the SDRAM Mode Register as well. One burst type is the sequential mode, while the other type is the interleaved mode. FIG. 1 is a table which demonstrates the differences between the two different burst modes having a burst length of 4. As is shown, the burst type determines the order of how the data is accessed dependent on the starting address. In the sequential mode the data is accessed in consecutive addresses, while in the interleaved mode only the higher or lower addresses are accessed first.
Implementing either burst type in a large SDRAM device such as a 256M chip, can be difficult and costly. This is because such devices require a very large architecture to support such a device.
It is therefore, an object of the present invention to provide an improved architecture that enables a SDRAM device to operate in the sequential burst mode without substantially increasing the size of the device.